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Corelis
offers free half day JTAG seminars in various locations and
free three-day training classes that include a boundary-scan tutorial
and hands-on lab exercises using Corelis ScanExpress
hardware and software. The training class covers all aspects of
boundary-scan testing using Corelis ScanExpress tools. Design
for testability (DFT), JTAG emulation functional test (JET),
in-system programming (ISP) and test procedure generation are
also covered.
The training includes a combination
of lectures, demonstrations, and hands-on exercises using actual
hardware to provide you with an overview of ScanExpress test and
ISP features and to have you run your own developed test. |
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Corelis Customer Training Class Schedule and Location
2009 Schedule:
January 13-15
February 10-12
March 17-19
April 21-23
May 12-14
June 17-19
July 14-16
August 11-13
September 22-24
October 13-15
November 10-12
Location: Corelis facility, 12607 Hiddencreek Way, Cerritos, CA
90703
Registration contact: Anita Pawlak, email:
anita@corelis.com,
Tel.: +1 (562) 926-6727 ext. 127
All Corelis Customer training
classes held at Corelis, are at NO CHARGE!
Who should attend?
This class is intended for design
engineers, test engineers, and managers who plan to use
boundary-scan test methodology and the Corelis ScanExpress family of
products. Previous knowledge of boundary-scan technology is not
required.
What will you be able to do upon completion
of the class?
Upon completion of the training you
will be able to correctly implement boundary-scan DFT and ISP
facilities into your new designs. You will also be able to
develop boundary-scan test procedures on your own as well as
in-system programming files for CPLDs and Flash memories.
Topics covered in the class
include:
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Introduction to boundary-scan
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Design for boundary-scan testability Guidelines
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Design for boundary-scan In-System Programming Strategy
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Test generation and testing
methods for boundary-scan-based designs
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Test program generation
methodology
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Test program execution plan
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Test program interactive
debugging concepts
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At-speed embedded functional
testing using an on-board JTAG-based CPU
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In-system programming of CPLDs
and Flash memories tutorial
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Hands-on individual lab exercises
using real units under test (UUTs) that will teach you:
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How to generate and execute
interconnect tests
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How to test memory interconnects
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How to test logic clusters
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How
to use an embedded processor’s JTAG port for embedded
functional testing
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How to program CPLDs and Flash
memories in circuit
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How to troubleshoot a test
procedure
You will become familiar with the
entire Corelis ScanExpress product family, including:
Schedule, Registration, Cancellation, and
General Information
For additional schedule and
registration information about
these seminars and training classes, please contact:
Anita Pawlak
anita@corelis.com
+1
(562) 926-6727 ext. 127
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Classes are subject to
cancellation two weeks prior to start date.
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Classes held at the Corelis
facility are no-charge.
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On-site training classes are
available. Contact your Corelis sales engineer or
sales@corelis.com for scheduling and pricing
information.
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