Boundary-Scan Test and In-System
Programming Software

Test Program Generation

The ScanExpressTPG™ Intelligent Test Pattern Generator is the next generation automatic boundary-scan test pattern generation tool that takes the process of boundary-scan automation to a new level of performance and ease of use. ScanExpressTPG automatically generates test patterns that facilitate the pin-level fault detection and isolation of all boundary-scan testable nets on a printed circuit board (PCB). ScanExpressTPG also creates test vectors to detect faults on the pins of non‑scannable components such as clusters and memories that are surrounded by scannable devices.  ScanExpressTPG accepts most industry recognized CAE/CAD netlists.

ScanExpressTPG provides an integrated development environment (IDE) system in which the user can generate boundary-scan tests from scratch, invoke the ScanPlusDFT Analyzer™ to produce test coverage reports, and invoke ScanExpress Runner™ to execute created tests, all from a single Graphical User Interface (GUI). The user starts with the basic board design files, adds supplemental information, generates test vectors, creates test coverage reports, and executes the tests by using the descriptive icons located on the shortcuts bar.

By utilizing ScanExpressTPG, both experienced and novice users can create boundary-scan test vectors in a fraction of the time it takes to develop these test vectors using legacy test pattern generators. Test development time is greatly reduced by automating and integrating many of the tasks that the user previously had to perform manually.

ScanExpressTPG greatly reduces the number of keystrokes and mouse clicks and eliminates text editing wherever possible. By maximizing the automation behind the complete process, boundary-scan test procedures can be developed with the least amount of time and effort while ensuring that the final test procedure is of the highest possible quality. For complete information on ScanPlusDFT Analyzer, please refer to the detailed data sheet for this product.

ScanExpressTPG also supports IEEE-1149.6 devices, hierarchical bridge devices (TI 8996 ASP, TI 8997 Scan Path Linker, SCANPSC110F, SCANSTA111, SCANSTA112, ScanBridge, etc) and BIST (Built-In-Self-Test).

ScanExpressTPG Main Window

Automatic Detection of the JTAG Scan Chain

Boundary-Scan Scripting

Boundary-scan scripting is a new feature that enables the user to create customized boundary-scan testing sessions. ScanExpress Runner DLL, Runner ETF files, ScanExpress Debugger DLL and cluster testing are now joined by a powerful script engine that supports even higher levels of test customization.

The new ScanExpressTPG and ScanExpress Runner tools now support integrated boundary-scan scripting capabilities which are available to customers with a valid support agreement at no additional charge.

ScanExpressTPG now incorporates a new GUI for creating and debugging script tests for use in ScanExpress Runner.

For example, boundary-scan scripting can be used to perform custom tests such as programming a special EEPROM device using a proprietary serial protocol, checking ADC readings within a valid range of values, testing custom memory not covered by a standard memory test, and saving user customized test data and messages to a log file.

Boundary-Scan Scripting

Test Coverage Analysis

ScanExpressDFT Analyzer calculates the test coverage of boards and systems that include a mix of boundary-scan and non-boundary-scan devices. It also helps design and test engineers to increase fault coverage and reduce boundary-scan test program development time.  The figure to the right depicts a ScanExpressDFT Analyzer screen. 

ScanExpressDFT Analyzer intelligently merges various testability reports generated by ScanExpressTPG and provides summary and detailed test coverage reports for the board. The combined test coverage reports help engineers to maximize the use of boundary-scan and reduce the need for "nails" access to nets and pins of the board under test.

ScanExpressDFT Analyzer is generally used after schematic capture and before PCB layout. At this stage of product development, ScanExpressDFT Analyzer can create a comprehensive test coverage reports that identifies all of the boundary-scan nets and pins and classifies them as completely tested, partially tested, or not tested. The report also recommends where to add test points (pads) for physical "nails" access if additional test coverage is required. For complete information on ScanExpressDFT Analyzer, please refer to the detailed data sheet for this product.

Test Coverage Summary Report

Test Program Execution

The ScanExpress system includes the ability to execute boundary-scan tests and perform In-System Programming in a pre-planned specific order called a test plan. Test vectors, in the form of Compact Vector Format (CVF) files which have been generated using ScanExpressTPG, can be automatically executed and the results displayed and logged to a file. Other formats such as SVF, JAM, STAPL, and J-Drive are also supported. Different test plans may be constructed for different UUT's. Tests within a test plan may be reordered, enabled or disabled. An unlimited number of different tests can be combined into a test plan. The software used to run these tests is ScanPlus Runner.

ScanExpress Runner includes a flexible test executive that is used to develop a test sequence or test plan from various independent tests. These test steps can then be executed sequentially, repeated any number of times or run continuously. The main features of the test executive are as follows:

• Utilizes test sequences based on Pass/Fail test results

• Enables test sequence debugging by forcing selected test steps to skip, stop on failure, or continue on failure

• Logs test results and reports (detailed and summary) to a file

• Prints test results

• Allows the operator to enter their name, UUT name, model number, serial number, etc. This is used for logging and reporting.

ScanExpress Runner gives the user an overview of all test steps and the results of executed tests. These results are displayed both for individual tests as well as for the total test runs executed. ScanPlus Runner provides the ability to add or ScanExpress various test steps from a test plan, or re-arrange the order of the test steps in a plan. Tests can also be enabled or disabled, and the test execution can be stopped upon the failure of any particular test. When a test fails, the user has the option to either accept the Passed/Failed results and continue testing other boards or display the cause of the failure as shown in the figure to the right.

Test and In-System-Programming Execution

Test Results Diagnostics Screen

Visual Fault Diagnostics

ScanExpress Viewer™ is a powerful Graphical Fault Identification System that helps to isolate the source and location of faults encountered during the manufacturing and design of printed circuit board (PCB) assemblies.

By combining the visual aspects of a photographic image of the PCB assembly with the detailed layout descriptions supplied by the board netlist and Boundary-Scan fault-report, a complete visual representation of the target system is created that facilitates the quick isolation of any failure under investigation.

With its easy-to-use interface, ScanExpress Viewer will allow even the most novice users, with little or no Boundary-Scan experience, the complete ability to pinpoint the exact source and location of PCB assembly failures. This is true for even the most complex boards and systems with faults not visible to the naked eye or easily detectable by traditional test methods.  In addition to its powerful usage during manufacturing, testing, and repair of PCB assemblies, ScanExpress Viewer offers a variety of features particularly suited for the design engineer. For complete information on ScanExpress Viewer, please refer to the detailed data sheet for this product.

In addition to automatically running the test steps, ScanExpress Runner can operate in a debug mode. In this mode the user can interactively perform vector single stepping, run to vector breakpoint, and loop on vectors in the Debug window. Any of these operations can be performed in either Pattern or Waveform mode. The debug mode is very useful for troubleshooting and determining the source of hard to find failures during test program development.

Debug information is displayed in Pattern and Waveform modes. The Figure to the right depicts the Debug window in Waveform mode.

Visual Fault Diagnostics

Low Level Debugging

Interactive Debugging

The ScanExpress Debugger™ is an excellent tool for engineers doing debug during prototype design verification and testing. It is very useful for finding shorts and opens on and between BGA devices and other fine-pitch components. The ScanExpress Debugger allows interactive control and observation of all the boundary-scan controllable inputs and outputs on a Unit Under Test (UUT). It can also apply data to inputs of clusters and read their responses if the cluster I/Os are accessible via boundary-scan components. The ScanExpress Debugger software includes an interactive Graphical User Interface (GUI), as shown below, that assists the user in setting and monitoring the state of pins on the UUT. A powerful Pin and Netlist browser with filtering and sorting capabilities allows you to easily select the pins and/or nets of interest and insert them into the main debug window for various data manipulation. All debug sessions can be saved and later recalled for reuse.

Interactive Debugging

ScanExpress Merge - System-Level Test

Until now, boundary-scan testing has been primarily used as a complete test and programming solution for single printed circuit board (PCB) assemblies. Now the use of boundary-scan testing can be easily extended to test systems that consist of multiple PCBs, treating them as a single, combined unit.

ScanExpress Merge can be used to combine multiple target assemblies into a single boundary-scan compatible target system. ScanExpress Merge has many applications, including:

• Motherboard and Daughter card(s) assembly testing

• Multiple card chassis testing

• Gang testing of multiple cards

One common application for ScanExpress Merge is the testing of Main and Daughter boards together as a combined assembly as shown in the figure on the right. Testing the three assemblies together and the interconnects between them increases the test coverage of the assemblies as a whole.  ScanExpress Merge can be used in a similar manner for any system topology.  By preprocessing the test data files of each of the assemblies, ScanExpress Merge generates a unified set of input files that are compatible with Corelis’ ScanExpressTPG Test Program Generator. ScanExpressTPG will automatically process the merged assemblies and generate test vectors for the entire combined system, thereby extending boundary-scan testing and programming to the system level. ScanExpress Merge provides an exceptionally easy-to-use set-up Wizard that contains step-by-step instructions to ensure the user to enter the correct data for each module.

ScanExpress Merge also automates the process of testing board IOs and traces that are connected to DIMM memory sockets and connectors. ScanExpress Merge combines the data of the board and the data of the ScanIO and ScanDIMM parallel IO modules into a single set of merged input files that are compatible with ScanExpressTPG. Adding support for boundary-scan parallel IO modules saves time by eliminating the need to describe the connections between the PCB connectors and the modules. To further simplify operations, ScanExpress Merge automatically adds a prefix to the names of items that are associated with each assembly such as net names, device identifiers, etc. This allows the user to uniquely identify each assembly within the combined system and to properly diagnose faults when the complete system is tested. The default prefix is optional for each of the merged assemblies and can be changed by the user.

When connecting boards using a connector that plugs directly into a mating connector, ScanExpress Merge automatically finds and connects the relevant nets on both sides of the connectors. The user is only required to specify which connector(s) are mated. This feature is very useful when using daughter cards that plug into motherboards or cards that plug into a backplane. In addition, ScanExpress Merge automatically generates connection lists for mated connectors and generates suggested wire lists for connectors that are selected by the user to connect to Corelis ScanIO modules. This allows an engineer to follow ScanExpress Merge’s recommended connection list rather than having to prepare the ScanIO-to-UUT connection list manually.

ScanExpress Merge Main Screen

Merging Modules into a Single Assembly