Design for Test Guidelines and Considerations

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Board-Level Design

Outline

• Schematic Design Considerations

  • JTAG Device Selection / Identification

  • Product Design

  • Memory Cluster Testing

  • Power Supply Loading
     

• FPGA Considerations
   

• Flash Programming Considerations
   

• PCB Layout Considerations

  • General

  • Component Placement

  • Trace Routing

  • Test Points

  • Multiple Scan-Chains

Schematic Design Considerations

• JTAG Device Identification

• Scan-Chain Design (see boundary-scan chain tips)

• TAP Interface Connector

• Board-Level DFT Design

JTAG Device Selection / Identification

• Datasheet indicates IEEE-1149.1, JTAG or boundary-scan compliance

• High pin count BGA or surface mount device
  (FPGA, CPLD, CPU, DSP)

• Pin names TCK, TMS, TDI, TDO and TRST_N

• BSDL file available

• Chip vendors such as Altera, AMCC, Atmel, Broadcom, Cypress, Freescale, IDT, Lattice, Marvell, Micron, National Semiconductor, QLogic, Samsung, ST Microelectronics, TI, Xilinx, and more

Design boundary-scan into the product, not as an afterthought

• Design engineers should think ahead about testing

• Utilize DFT guidelines prior to and during board layout

• Identify up front whether devices have BSDL files available and ensure they have been tested

• Consider the initial power-up or reset state of board

• Ensure scan-chain is operational when power is applied

  • Properly terminate compliance enable pins

  • CPLDs that control power logic or scan-chain paths must remain in BYPASS

  • TRST* pins must be high for JTAG testing

  • Constraints cannot be used if the scan-chain is not working

• Tri-state or disable non-boundary-scan devices

  • Provide boundary-scan control to disable device outputs that will otherwise conflict with nets involved in boundary-scan test (enable pins, test pins, reset signals, power shutdown circuitry)

• Disable these devices by:

  • Connecting a boundary-scan controllable output on the net to control the chip enable of the conflicting device (FIXED_HIGH, FIXED_LOW constraint)

  • Installing a dedicated jumper which put the target into a boundary-scan ready state

  • Connecting a GPIO pin available on Corelis JTAG controllers to the offending one

   

Considerations for memory cluster testing

• Memory cluster tests are performed by controlling the pins on the memory device using surrounding JTAG logic including address pins, data pins, chip select/enable, output enable, RAS (DRAM), CAS (DRAM), clock (synchronous devices), write strobe (FIFO), read strobe (FIFO), and write enable

• The driving boundary-scan devices must have separate control cells for the address, data, and control pins on the memory device

  • Some CPU devices have shared control cells

  • The BSDL file contains this information

• JTAG control of the clock signals must be provided

  • Ensure the clock pin has a JTAG output cell to drive the clock

  • Pins identified in the BSDL file cannot drive test patterns

  • If a PLL is used to drive the clock, ensure the PLL has a bypass feature that can be used during JTAG testing

  • The PLL bypass feature should be controllable using JTAG

    • Note some PLLs enable bypass by grounding the AVDD pin

  • Adding stubs to the clock net may alter the functional operation of the circuit

  • Memories can be functionally tested at-speed if they are connected to a supported EJTAG CPU

  • Utilize ScanExpress JET to test the memory if it is connected to a supported CPU (contact Corelis for a current list)

   

Consider Power Supply Loading

• The UPDATE-DR state on all components can induce large current swings and ground bounce

  • Ensure the power supply and voltage regulators can handle JTAG test current

  • Turn up the current limit. Functional current and boundary-scan test current requirements may widely differ

  • BYPASS can be used to remove components from the test

  • Identify low impedance pull-up and pull-down resistors, especially digitally controlled impedance (DCI) nets

  • Zero ohm resistors should be marked transparent
     

Xilinx and Altera FPGA Considerations

• Xilinx and Altera FPGA devices have different test characteristics depending on if the devices are configured

• Maximum testability on these devices is in the pre-configuration state

• To keep Xilinx parts in pre-configuration mode, the INIT* pin needs to be held low prior to and during power-up of the target

• To keep Altera parts in pre-configuration mode, the NCONFIG* pin needs to be held low prior to and during power-up of the target

• Recommend these pins route to the TAP header in place of a ground pin. When the JTAG controller plugs into the TAP, the pin will automatically be pulled low

Compliance Enable Pins Must Be Satisfied

• Compliance pin states are listed in the BSDL file

• Correct compliance pin states must be maintained prior to and during JTAG testing to maintain test compliance

• For example, the BSDL file for the Motorola MPC106 device describes the following compliance enable pin:
  
  attribute COMPLIANCE_PATTERNS of mpc106: entity is "(LSSD_MODE_L) (1)";
  
  indicates that pin LSSD_MODE_L must be a logic high prior to and during boundary-scan testing for correct JTAG operation
   

Considerations for Flash In-System Programming

• In-system programming of flash devices through JTAG is done by emulating read & write cycles to the flash device using surrounding JTAG logic including address pins, data pins, chip enable, output enable, write enable, and optionally reset, write protect and ready/busy

• The driving boundary-scan devices must have separate control cells for the address, data, and control pins on the memory device

• To reduce programming time:

  • Utilize boundary-scan devices with faster TCK rates

  • Ensure that your scan-chain is short

  • Remove unnecessary constraints

  • Use external write strobe

• External Write Strobe (Flash In-System Programming)

  • The WRITE_STROBE* signal is active low and should be pulled high with a 1K resistor on the target board. It should be logically OR-ed with the WRITE_ENABLE* signal so that assertion of either the WRITE_ENABLE* signal or the WRITE_STROBE* signal will assert the flash WE* pin

Flash In-System Programming Theoretical Speed Formula

(#bits in chain) * (#scans/write) * (#writes/location) * (#locations)
                                      TCK frequency

Where:
#bits in chain - effective length of the boundary-scan chain (assuming unused components are placed in BYPASS)
#scans/write - number of DR scans which are required in order to write a data value to the flash
#writes/location - number of data values that must be written to program each location
#locations - number of data locations to be programmed
TCK frequency - frequency of the JTAG test clock (TCK) signal

PCB Layout Considerations

• Component Placement

• Trace Routing

• Test Points

• Multiple Scan-Chains

General

• TCK needs to be as free as possible of glitches and spikes, since all
  operations are triggered by rising and falling TCK edges.

• Connection of TDO of last device in scan chain to board TDO should be as
  short as possible.

• TCK and TMS fan out to every device is most critical.

• When using fan out buffers to distribute TCK, TMS and TRST_N, put
  termination resistors on the primary side of the buffer (signals coming
  from the JTAG controller) .

• A series resistor on the TDO of the last device in the chain should be close
  to that device’s TDO pin.

Component Placement

• Provide adequate room around the TAP connector to plug the cable in

  • Consider cable access when the product is enclosed or fully assembled

• Easier debug access when termination resistors are placed consistently close to the TAP connector along with a clearly labeled ground point

• Do not place the TAP connector near noisy analog components such as voltage regulators

• Consider access to probe the scan-chain if things don’t work

• Place JTAG devices such that a star topology can be implemented on the JTAG signals

Trace Routing

• Recommend general documented layout guidelines such as

  • A Practical Guide to High-Speed PCB Layout, Analog Devices

  • Guidelines for Designing High-Speed FPGA PCBs, Altera

  • High-Speed Board Layout Guidelines, Altera

  • Basic Principals of Signal Integrity, Altera

• Recommend JTAG traces be a minimum 10 mil width with minimum 10 mil spacing with length as short as possible JTAG signals should be routed on the outer layers away from noisy analog voltage regulators 36

• TMS and TCK are broadcast lines. They should be routed in accordance to high-frequency bus rules. Use fan out buffers to avoid overload of TMS and TCK signals coming from the JTAG controller.

• Route TCK and TMS in a star topology

• Signal quality is a key factor for successful JTAG testing

  • JTAG test signals should be assigned as critical for first pass route

  • Most common problems are reflections and ringing on TCK

  • Faster TCK results in faster in-system programming times

Test Points

• Compliance enable pins should be accessible. It is a good idea to place pads for both pull-up and pull-down resistors on the pin when in doubt

• Even though TDI and TDO are point to point, consider an accessible test point at each link for debug if required

• Always ensure there are convenient test point locations for ground

  • Debug is much easier with the ability to clip one lead to ground

Multiple Scan-Chains

• A working scan-chain should be one of the highest priorities

• Breaking up a scan-chain may provide easier debug capability

• Different groups use the JTAG chain differently

  • Designers need JTAG for in-circuit emulation and in-system programming

  • Test engineers need JTAG for interconnect testing

For more tips on boundary-scan chains, see boundary-scan chain tips.

 

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